System C Support in LegUp

By Zhi Li,

High-level synthesis using C++ works very well for designers describing data-flow applications like digital signal processing or video/image processing. But for certain control heavy applications, such as a bus controller, a designer will have trouble describing the cycle accurate behavior of the hardware in C++. We decided to help fix this problem by adding support for System C as an input language to LegUp HLS.

System C is a standard C++ library that allows a designer to specify cycle-accurate behavior. Typically System C is used for system-level modeling of a larger system. System C offers the advantage of faster simulation time than running RTL simulations while still being able to measure cycle-accurate behavior.

System C explicitly describes the cycle behavior of the application. There is no flexibility for the operations to be scheduled into different clock cycles like when C++ is used in LegUp HLS. This provides the user with very fine-grained control over the behavior of the generated hardware.

AHB-Lite Bus Slave Controller Example

For an example of a control-heavy application, we will implement a simplified AHB-Lite bus slave controller in System C. We will focus on how to implement the part of the bus protocol that requires cycle-accurate control: the error response code.

For background, the AHB-Lite bus protocol has two possible responses (HRESP) from the slave to the master. First, if the transaction was successful the HRESP will be OKAY (0) but if there was an error there will be a two cycle delay and HRESP will be ERROR (1). See the waveforms below:

AHB-Lite HRESP Error

Figure 1: AHB-Lite HRESP Error Response (Image source: AMBA 3 AHB-Lite 1.0 Spec)

 

The 2-cycle delay behavior when an error occurs is hard for a designer to express in typical LegUp HLS C++ code. But with System C, we can use the wait() function to introduce a 1-cycle delay.
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LegUp 7.3 Release

By Zhi Li,

We are excited to announce that LegUp 7.3 has been released! You can download LegUp here.

Release Notes

New features, enhancements and bug fixes for this release:

  • Added alpha support for System C. Check out our blog post for more details.
  • Added support for ap_int type (arbitrary bitwidth for signed integers, previously only unsigned integers were supported for arbitrary bitwidth)
  • Improvements to the LegUp GUI
  • Various bug fixes.

Pricing

LegUp 7.3 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at sales@legupcomputing.com.

Download

You can download LegUp here.

LegUp 7.2 Release

By Ruolong Lian,

We are excited to announce that LegUp 7.2 has been released! You can download LegUp here.

Release Notes

New features, enhancements and bug fixes for this release:

  • Added support to use Xilinx’s XSIM simulator for Hardware simulation and Software/Hardware co-simulation.
  • Integrated Xilinx LogiCORE Floating-Point Operator IPs for implementing floating-point operations on Xilinx FPGAs.
    • The two features above are only available when targeting Xilinx devices, and require users to install the Vivado design suite separately.
  • Various bug fixes.

Pricing

LegUp 7.2 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at sales@legupcomputing.com.

Download

You can download LegUp here.

LegUp Booth at the Design Automation Conference (DAC 2019)

By Jongsok Choi,

LegUp will be exhibiting at the Design Automation Conference (DAC) in Las Vegas, Nevada from June 3-5. Come visit us at booth number 1127!

We will be showcasing LegUp’s industry leading high-level synthesis software and talking about the next generation of our tools. We will also have live computer vision demonstrations designed with LegUp HLS and targeting various FPGA devices.

https://dac.com/sites/default/files/56dac_logo_lg_1024x5001.png

dac1

dac2

More updates to come next week!

LegUp Computing presents at Intel Capital Summit

By Andrew Canis,

Andrew Canis our CEO attended the Intel Capital Summit in April, 2019 and he gave an elevator pitch talking about LegUp Computing. We really appreciate all the support from our investor Intel Capital.

Check out the video below:

LegUp Computing Inc. provides an integrated development environment that enables hardware designers to program any FPGA device in C/C++ for greater productivity and easier verification.

Please contact us at info@legupcomputing.com if you’re interested in hearing more!

LegUp 7.1 Release

By Ruolong Lian,

We are excited to announce that LegUp 7.1 has been released! You can download LegUp here.

Release Notes

New features, enhancements and bug fixes for this release:

  • AXI slave interface now supports concurrent access while the accelerator is running.
  • Added a  “stable” argument interface type of which LegUp will assume the signal is stable and remove unnecessary registers.
  • Improved timing constraint adjustment for achieving a better pipeline initiation interval (II).
  • Added support to convert global memory accesses to registers when it’s safe. This helps relaxing the resource constraint of BRAM ports to achieve better II.
  • Sped up pipeline scheduler especially for large pipelines.

Pricing

LegUp 7.1 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at sales@legupcomputing.com.

Download

You can download LegUp here.

LegUp 7.0 Release

By Ruolong Lian,

We are excited to announce that LegUp 7.0 has been released! You can download LegUp here.

Release Notes

New features, enhancements and bug fixes for this release:

  • Extended support for versatile C++ software testbench that can be used for Hardware/Software co-simulation.
  • Improved HLS compilation run-time especially for large input programs.
  • Various QoR enhancements for pipelined circuits:
    • Register usage reduction via intelligent use of MLAB/SLICEM, especially for deep pipelines.
    • Control logic optimization that leads to better initiation interval (II), Fmax, and area.
    • Fmax improvement for circuits with large initiation interval (II).
  • Enhanced strength reduction for integer multiplications.
  • Reduced RAM usage for different FPGA vendors.
  • Various bug fixes.

Pricing

LegUp 7.0 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at sales@legupcomputing.com.

Download

You can download LegUp here.

University of Toronto True Blue Expo

By Andrew Canis,

Thanks to everyone who came by and visited out booth at MaRS for the University of Toronto startup showcase! We really enjoyed talking about how LegUp Computing’s technology makes FPGAs much easier to program. I was amazed at how many startups are being spun out of the University of Toronto. We appreciate the support from the UTEST incubator and University of Toronto as we grow the company.

Blue Expo Booth

LegUp 6.7 Release

By Ruolong Lian,

We are excited to announce that LegUp 6.7 has been released! You can download LegUp here.

Release Notes

New features and bug fixes for this release:

  • Automatic loop nest merge (loop coalescing) to reduce loop nest overhead and enhance loop pipeline throughput.
  • Improved support of the floating-point multiply-accumulate mode of Intel’s hard floating-point DSP core.
  • Improved optimization for bit-level operations.
  • Added legup_reg() primitive function (template <typename T> T legup_reg(T in);) to allow explicit register insertion.
  • Support write strobe signal (WSTRB) in the auto-generated AXI4 slave interface.
  • Up to 14x faster HW/SW Co-simulation of AXI4 slave interface.
  • Support for Microsemi Libero 12.0.
  • Various bug fixes

Pricing

LegUp 6.7 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at sales@legupcomputing.com.

Download

You can download LegUp here.

LegUp Seminar Talk at the University of Toronto

By Andrew Canis,

Our CEO and CTO, Andrew Canis and Jongsok Choi, gave a talk at the monthly FPGA seminar at the University of Toronto last week. We started with an overview of LegUp Computing and how FPGAs compare to CPUs. We talked about how our LegUp high-level synthesis software tool makes FPGA design easier by allowing a C/C++ input language even for system-level design. We showed off some surprising results we found for floating point cores generated with LegUp HLS compared to hand-written RTL cores. Then we showed a demo of our Memcached F1 instance using cloud FPGAs on AWS, and we gave some highlights on what it’s like to working at a startup.

Check out the youtube video of the talk below (sorry for the poor audio quality). The slides are available here.

 

If you like what you heard and you want to join our engineering team working on cutting edge FPGA technology, please check out our career page and email us at jobs@legupcomputing.com!